luca-valente

culsans

Tightly-coupled cache coherence unit for CVA6 using the ACE protocol

cva6

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

hero

Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and an application-class host CPU, including full-stack software and hardware.

luca-valente.github.io

opensbi

RISC-V Open Source Supervisor Binary Interface

rv_plic

Implementation of a RISC-V-compatible Platform Interrupt Controller (PLIC)

sv_exercise

cva6

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

axi

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

pulp

This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain accelerated by a PULP cluster with 8 cores.

luca-valente/culsans

Tightly-coupled cache coherence unit for CVA6 using the ACE protocol

luca-valente/cva6

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

luca-valente/hero

Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and an application-class host CPU, including full-stack software and hardware.

luca-valente/luca-valente.github.io

luca-valente/opensbi

RISC-V Open Source Supervisor Binary Interface

luca-valente/rv_plic

Implementation of a RISC-V-compatible Platform Interrupt Controller (PLIC)

luca-valente/sv_exercise