Example project for a 4x4-bit Booth multiplier implementation using an Atlys Spartan-6 FPGA Trainer Board.
Note: As of this writing, the board is listed as a legacy product and with limited production.
The algorithm was developed by Andrew D. Booth and published for the first time in an article in The Quarterly Journal of Mechanics and Applied Mathematics in 1951. The algorithm was developed in a time where calculators were faster doing shift operations than sums.
More details on the algorithm can be found in the documentation.
A short video showing the multiplier working can be found here.
