Pinned Repositories
cs3220-labs
DNN_NeuroSim_V1.3
Benchmark framework of compute-in-memory based accelerators for deep neural network (inference engine focused)
dummy_vip
Files for the IP Integration Exercise
FedML
FedML: A Research Library and Benchmark for Federated Machine Learning
hwpe-ctrl
IPs for control-plane integration of Hardware Processing Engines (HWPEs) within a PULP system
kernel-prediction-networks-PyTorch
Reimplement of 'Burst Denoising with Kernel Prediction Networks' and 'Multi-Kernel Prediction Networks for Denoising of Image Burst' by using PyTorch
learning-to-learn
Learning to Learn in TensorFlow
luke-avionics.github.io
networkx
Network Analysis in Python
SkyNet
luke-avionics's Repositories
luke-avionics/SkyNet
luke-avionics/cs3220-labs
luke-avionics/DNN_NeuroSim_V1.3
Benchmark framework of compute-in-memory based accelerators for deep neural network (inference engine focused)
luke-avionics/dummy_vip
Files for the IP Integration Exercise
luke-avionics/FedML
FedML: A Research Library and Benchmark for Federated Machine Learning
luke-avionics/hwpe-ctrl
IPs for control-plane integration of Hardware Processing Engines (HWPEs) within a PULP system
luke-avionics/kernel-prediction-networks-PyTorch
Reimplement of 'Burst Denoising with Kernel Prediction Networks' and 'Multi-Kernel Prediction Networks for Denoising of Image Burst' by using PyTorch
luke-avionics/learning-to-learn
Learning to Learn in TensorFlow
luke-avionics/luke-avionics.github.io
luke-avionics/networkx
Network Analysis in Python
luke-avionics/pulp-runtime
Simple runtime for Pulp platforms
luke-avionics/pulp_soc
luke-avionics/pulpissimo
This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.
luke-avionics/pytorch_geometric
Graph Neural Network Library for PyTorch
luke-avionics/Pyverilog
Python-based Hardware Design Processing Toolkit for Verilog HDL
luke-avionics/SIGMA
RTL implementation of Flex-DPE.
luke-avionics/sw
PULPissimo, PULP-SDK and PULP-RUNTIME exercises
luke-avionics/verilog-axis
Verilog AXI stream components for FPGA implementation
luke-avionics/wide_alu