Pinned Repositories
luogantt's Repositories
luogantt/verilog-demo
luogantt/my_blog
luogantt/BELLE
BELLE: Be Everyone's Large Language model Engine（开源中文对话大模型）
luogantt/openISP
Image Signal Processor
luogantt/alpaca-lora
Instruct-tune LLaMA on consumer hardware
luogantt/ASRT_SpeechRecognition
A Deep-Learning-Based Chinese Speech Recognition System 基于深度学习的中文语音识别系统
luogantt/core-v-mcu
This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.
luogantt/cva6
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
luogantt/CyberRT
Baidu Apollo(v8.0.0) CyberRT Framework CMake Build
luogantt/DeepSpeed
DeepSpeed is a deep learning optimization library that makes distributed training and inference easy, efficient, and effective.
luogantt/deepstream_reference_apps
Samples for TensorRT/Deepstream for Tesla & Jetson
luogantt/dRehmFlight
Teensy/Arduino flight controller and stabilization for small-scale VTOL vehicles
luogantt/Gumption-Trap-
This project is an autonomous solar powered boat which drives around following gps coordinates and plots the depth of water with sonar
luogantt/iob-cache
Verilog configurable cache
luogantt/LibRaw
LibRaw is a library for reading RAW files from digital cameras
luogantt/Livox-Mapping
An all-in-one and ready-to-use LiDAR-inertial odometry system for Livox LiDAR
luogantt/ORB_SLAM3_detailed_comments
Detailed comments for ORB-SLAM3
luogantt/PathPlanning
Common used path planning algorithms with animations.
luogantt/riscv-gnu-toolchain
GNU toolchain for RISC-V, including GCC
luogantt/ros_project
luogantt/scr1
SCR1 is a high-quality open-source RISC-V MCU core in Verilog
luogantt/so-vits-svc-fork
so-vits-svc fork with realtime support, improved interface and more features.
luogantt/Systolic-array-implementation-in-RTL-for-TPU
IC implementation of Systolic Array for TPU
luogantt/TensorRT-Alpha
🔥🔥🔥TensorRT-Alpha supports YOLOv8、YOLOv7、YOLOv6、YOLOv5、YOLOv4、v3、YOLOX、YOLOR...🚀🚀🚀CUDA IS ALL YOU NEED.🍎🍎🍎It also supports end2end CUDA C acceleration and multi-batch inference.
luogantt/tensorrtx
Implementation of popular deep learning networks with TensorRT network definition API
luogantt/USTC-RVSoC
An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V CPU+SoC，包含一个简单且可扩展的外设总线。
luogantt/verilog-axi
Verilog AXI components for FPGA implementation
luogantt/vroom
VRoom! RISC-V CPU
luogantt/wenet
Production First and Production Ready End-to-End Speech Recognition Toolkit
luogantt/yolov5
YOLOv5 🚀 in PyTorch > ONNX > CoreML > TFLite