Pinned Repositories
aes_128
AES (Rijndael) IP Core (128 bit version)
cores
Various HDL (Verilog) IP Cores
corundum
Open source, high performance, FPGA-based NIC
CSerialPort
CSerialPort - lightweight cross-platform serial port library for C/C++/C#/Java/Python/Node.js
darkriscv
opensouce RISC-V implemented from scratch in one night!
dsi_controller
MIPI DSI controller
GitHub520
:kissing_heart: 让你“爱”上 GitHub，解决访问时图裂、加载慢的问题。（无需安装）
hdmi
Send video/audio over HDMI on an FPGA
MIPI
MIPI_CSI2_TX
VHDL code for using Xilinx MGT gigabit transceivers/LVDS lines for MIPI CSI-2 TX protocol
luoheng1208's Repositories
luoheng1208/aes_128
AES (Rijndael) IP Core (128 bit version)
luoheng1208/cores
Various HDL (Verilog) IP Cores
luoheng1208/corundum
Open source, high performance, FPGA-based NIC
luoheng1208/CSerialPort
CSerialPort - lightweight cross-platform serial port library for C/C++/C#/Java/Python/Node.js
luoheng1208/darkriscv
opensouce RISC-V implemented from scratch in one night!
luoheng1208/dsi_controller
MIPI DSI controller
luoheng1208/GitHub520
:kissing_heart: 让你“爱”上 GitHub，解决访问时图裂、加载慢的问题。（无需安装）
luoheng1208/hdmi
Send video/audio over HDMI on an FPGA
luoheng1208/MIPI
luoheng1208/MIPI_CSI2_TX
VHDL code for using Xilinx MGT gigabit transceivers/LVDS lines for MIPI CSI-2 TX protocol
luoheng1208/MIPI_CSI_2
luoheng1208/mipi_csi_receiver_FPGA
MIPI CSI-2 Camera Sensor Receiver verilog HDL implementation For any generic FPGA. Tested with IMX219 on Lattice MachXO3LF. 2Gbps UVC Video Stream Over USB 3.0 with Cypress FX3
luoheng1208/myhdl
The MyHDL development repository
luoheng1208/picorv32
PicoRV32 - A Size-Optimized RISC-V CPU
luoheng1208/prjxray
Documenting the Xilinx 7-series bit-stream format.
luoheng1208/riffa
The RIFFA development repository
luoheng1208/Serial-Studio
Multi-purpose serial data visualization & processing program
luoheng1208/smartcam
luoheng1208/timespec
Functions for working with timespec structures
luoheng1208/usb2_dev
USB 2.0 Device IP Core
luoheng1208/USB3_MIPI_CSI2_RX_V2_Crosslink_NX
MIPI CSI-2 Camera Sensor Receiver V2 Verilog HDL implementation For any generic FPGA. Tested with IMX219 IMX477 on Lattice Crosslink NX with Hard MIPI PHY. Gbps UVC Video Stream Over USB 3.0 with Cypress FX3, Currently WIP
luoheng1208/verilog-axi
Verilog AXI components for FPGA implementation
luoheng1208/verilog-axis
Verilog AXI stream components for FPGA implementation
luoheng1208/verilog-ethernet
Verilog Ethernet components for FPGA implementation
luoheng1208/verilog-pcie
Verilog PCI express components