lvcargnini

www.linkedin.com/in/lvcargnini @OpenPOWERFoundation

Samsung Semiconductor Inc. - DSRA/MSL/ R&DUSA

Pinned Repositories

agnoster-zsh-theme
A ZSH theme designed to disclose information contextually, with a powerline aesthetic
Language:Shell0 2 00
arachne-pnr
Place and route tool for FPGAs
Language:C++0 2 00
ariane
Ariane is a 6-stage RISC-V CPU
Language:SystemVerilog0 2 00
atom
:atom: The hackable text editor
Language:JavaScript0 2 00
berkeley-hardfloat
Language:Scala00
berkeley-softfloat-3
SoftFloat release 3
Language:C00
Blaster
Language:C++0 1 00
chisel-bootcamp
Generator Bootcamp Material: Learn Chisel the Right Way
Language:Jupyter Notebook0 2 00
fpu
synthesiseable ieee 754 floating point library in verilog
Language:Verilog2 2 00
systemverilog_language_plugin
Language:Java1 2 00

lvcargnini's Repositories

lvcargnini/fpu
synthesiseable ieee 754 floating point library in verilog
Language:Verilog2 2 00
lvcargnini/systemverilog_language_plugin
Language:Java1 2 00
lvcargnini/agnoster-zsh-theme
A ZSH theme designed to disclose information contextually, with a powerline aesthetic
Language:Shell0 2 00
lvcargnini/ariane
Ariane is a 6-stage RISC-V CPU
Language:SystemVerilog0 2 00
lvcargnini/atom
:atom: The hackable text editor
Language:JavaScript0 2 00
lvcargnini/Blaster
Language:C++0 1 00
lvcargnini/CryptRaider
Learnign to code for Unreal 5
lvcargnini/embench-iot
The main Embench repository
Language:Makefile1 0
lvcargnini/fpnew
[UNRELEASED] Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
Language:SystemVerilog2 0
lvcargnini/grift
Galois RISC-V ISA Formal Tools
Language:Haskell
lvcargnini/growl
The ultimate Notiication System for OS X
Language:Objective-C2 0
lvcargnini/klayout
KLayout Main Sources
Language:C++2 0
lvcargnini/linux-pine64
Linux Kernel for Pine64 Board
Language:C2 0
lvcargnini/llvm
Mirror of official llvm git repository located at http://llvm.org/git/llvm. Updated every five minutes.
Language:LLVM2 0
lvcargnini/llvm-project
This is the canonical git mirror of the LLVM subversion repository. Please see http://llvm.org/ for instructions on contributing to LLVM.
Language:C++2 0
lvcargnini/mesim
Memory Simulator
Language:C++2 0
lvcargnini/omnixtend-1
OmniXtend cache coherence protocol
Language:TeX1 0
lvcargnini/OpenSTA
OpenSTA engine
Language:C++1 0
lvcargnini/powerline
Powerline is a statusline plugin for vim, and provides statuslines and prompts for several other applications, including zsh, bash, tmux, IPython, Awesome and Qtile.
Language:Python2 0
lvcargnini/riscv-gnu-toolchain
GNU toolchain for RISC-V, including GCC
Language:C2 0
lvcargnini/riscv-tools
RISC-V Tools (GNU Toolchain, ISA Simulator, Tests)
Language:Shell2 0
lvcargnini/rv8
RISC-V simulator for x86-64
Language:C++2 0
lvcargnini/rv_plic
Implementation of a RISC-V-compatible Platform Interrupt Controller (PLIC)
Language:SystemVerilog2 0
lvcargnini/scr1
SCR1 is a high-quality open-source RISC-V MCU core in Verilog
Language:SystemVerilog1 0
lvcargnini/SuperScalar-RISCV-CPU
super-scalar out-of-order rv32imc cpu core, 4.2/2.3 DMIPS/MHz, 2/3-stage
Language:SystemVerilog1 0
lvcargnini/swerv_eh1
A directory of Western Digital’s RISC-V SweRV Cores
Language:SystemVerilog2 0
lvcargnini/tensorflow
An Open Source Machine Learning Framework for Everyone
Language:C++1 0
lvcargnini/testingGHEDA
Testing GitHub automation on EDA
lvcargnini/ToonTanks
Project used to learn Unreal Engine with C++
Language:HTML1 0
lvcargnini/WarehouseWreckage
Learnign to use Asseets and Player Control on Unreal 5
1 0