lvtoto

lvtoto's Stars

• westerndigitalcorporation/swerv_eh1

  A directory of Western Digital’s RISC-V SweRV Cores

  Language:SystemVerilog856131

• soDLA-publishment/soDLA

  Chisel implementation of the NVIDIA Deep Learning Accelerator (NVDLA), with self-driving accelerated

  Language:Verilog22249

• Lingrui98/RISC-V-book

  A translation project of the RISC-V reader

  17442

• Tencent/PocketFlow

  An Automatic Model Compression (AutoMC) framework for developing smaller and faster AI applications.

  Language:Python2.8k490

• xfguo/riscv-openwrt-port

  RISC-V OpenWrt Port

  Language:Makefile183

• doonny/PipeCNN

  An OpenCL-based FPGA Accelerator for Convolutional Neural Networks

  Language:C1.3k369

• SI-RISCV/e200_opensource

  Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2

  Language:Verilog2.6k1k

• OpenDLA/OpenDLA

  A discussion group on Open Source Deep Learning Accelerator, with technical reports and potential hardware/software issues.

  13839

• cluelogic/cluelib

  A generic class library in SystemVerilog

  Language:HTML7939

• PerfXLab/embedded_ai

  20936

• Intel-Media-SDK/MediaSDK

  The Intel® Media SDK

  Language:C++940460

• hardenedlinux/embedded-iot_profile

  embedded-iot_profile

  9826

• webmproject/libvpx

  Mirror only. Please do not send pull requests.

  Language:C899341

• DingGuodong/LinuxBashShellScriptForOps

  Linux Bash Shell Script and Python Script For Ops and Devops

  Language:Python449311

• openhwgroup/cv32e40p

  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

  Language:SystemVerilog966424

• ridecore/ridecore

  RIDECORE (RIsc-v Dynamic Execution CORE) is an Out-of-Order RISC-V processor written in Verilog HDL.

  Language:Verilog33064

• tesseract-ocr/tesseract

  Tesseract Open Source OCR Engine (main repository)

  Language:C++62.8k9.5k

• pulp-platform/pulpino

  An open-source microcontroller system based on RISC-V

  Language:C904298

• riscv-software-src/riscv-tools

  RISC-V Tools (ISA Simulator and Tests)

  Language:Shell1.1k447

• kailashahirwar/cheatsheets-ai

  Essential Cheat Sheets for deep learning and machine learning researchers https://medium.com/@kailashahirwar/essential-cheat-sheets-for-machine-learning-and-deep-learning-researchers-efb6a8ebd2e5

  15.1k3.4k

• kalcaddle/KodExplorer

  A web based file manager,web IDE / browser based code editor

  Language:PHP6.3k1.8k

• syntacore/scr1

  SCR1 is a high-quality open-source RISC-V MCU core in Verilog

  Language:SystemVerilog874277

• Digilent/vivado-boards

  Language:Tcl403214

• RoaLogic/adv_dbg_if

  Universal Advanced JTAG Debug Interface

  Language:SystemVerilog1711

• thingsboard/thingsboard

  Open-source IoT Platform - Device management, data collection, processing and visualization.

  Language:Java17.7k5.2k

• terryum/awesome-deep-learning-papers

  The most cited deep learning papers

  Language:TeX25.5k4.5k

• sifive/freedom

  Source files for SiFive's Freedom platforms

  Language:Scala1.1k286

• chipsalliance/rocket-chip

  Rocket Chip Generator

  Language:Scala3.3k1.1k

• nissl-lab/npoi

  a .NET library that can read/write Office formats without Microsoft Office installed. No COM+, no interop.

  Language:C#5.7k1.4k

• liuchengxu/space-vim

  :four_leaf_clover: Lean & mean spacemacs-ish Vim distribution

  Language:Vim Script2.9k254