High-Level Synthesis Performance Prediction using GNNs: Benchmarking, Modeling, and Advancing
Table of Contents
- About the Project
- Benchmarking
- Modeling and Advancing
- Toy Examples and Visualization
- Prerequisites
- Road Map
About The Project
This project aims to explore the capability of GNN-based predictors in HLS design performance evalution, where the ultimate goal is to provide fast and accurate circuit quality evaluation from early design stages as well as to facilitate hardware agile design.
Contribution
- Benchmarking: we build a standard benchmark containing 40k C synthesizable programs, which includes both synthetic programs and three sets of real-world HLS benchmarks. Each program is implemented on FPGA to generate ground-truth performance metrics.
- Modeling: we formally formulate the HLS performance prediction problem on graphs, and propose multiple modeling strategies with GNNs that leverage different trade-offs between prediction timeliness (early/late prediction) and accuracy.
- Advancing: we further propose a novel hierarchical GNN that does not sacrifice timeliness but largely improves prediction accuracy, significantly outperforming HLS tools
The papers related to this project
- DAC 2022: High-Level Synthesis Performance Prediction using GNNs: Benchmarking, Modeling, and Advancing
- More statistics of the benchmark: Program-to-Circuit: Exploiting GNNs for Program Representation and Circuit Translation
Benchmarking
Synthetic data
- Synthetic C programs are generated by ldrgrn.
- Our scripts of program generation, HLS execution, and FPGA implementation
Real-case data
We currently consider three mainstream benchmarks in HLS to build our real-case CDFGs.
Raw data files
The raw data files (i.e., C programs, extracted intermediate files from the HLS tool, and post-implementation resource usage and timing) are included in the folder Graphs, which are applicable for various feature engineering.
Processed datasets
The processed datasets are stored together with GNN models.
Modeling and Advancing
- The three approaches explored in our paper:
- 14 GNN models are profiled for graph-level regression of resource usage and timing
- 4 GNN models are explored for node-level classification of resource types
Toy Examples and Visualization
- Several toy examples are presented for better understanding: toy programs, the corresponding intermediate files after HLS front-end compilation, and the visualization of toy graphs.
- Visualization of all DFGs, CDFGs, and real-case applications are included for more intuitive understanding of IR graphs used in HLS design development.
Prerequisites
- Program generation: if no new synthetic program is desired, there is no need to install ldrgrn.
- HLS and FPGA implementation: if no new data instance is desired, there is no need to install Vivado Design Suite.
- Pytorch Geometric for graph-level regression tasks
- OGB for node-level classification tasks
Road Map
