/tdc-core

A 26ps RMS time-to-digital converter (TDC) core for Spartan-6 FPGAs

Primary LanguageVerilog

Time to Digital Converter core for Spartan-6 FPGAs
==================================================

Directory organization:
   core/            VHDL sources of the TDC core.
   demo/            Demonstration design for the SPEC board.
   doc/             Documentation.
   hostif/          Optional host interface.
   tb/              Test benches.