Pinned Repositories
2022-Machine-Learning-Specialization
book
datastructs_and_algorithm
Data struct and algorithm introduction and implementation in C/C++/Java.
gem5
This is an read-only mirror of the gem5 simulator. The upstream repository is stored in https://gem5.googlesource.com, code reviews should be submitted to https://gem5-review.googlesource.com/. The mirrors are synchronized every 15 minutes.
graphBIG
A Comprehensive Benchmark Suite for Graph Computing
GRIM
Source code of the processing-in-memory simulator used in the GRIM-Filter paper published at BMC Genomics in 2018: "GRIM-Filter: Fast Seed Location Filtering in DNA Read Mapping using Processing-in-Memory Technologies" (preliminary version at https://arxiv.org/pdf/1711.01177.pdf)
HMC-MAC
Processing-in Memory Architecture for Multiply-Accumulate Operations with Hybrid Memory Cube
IMPICA
This is a processing-in-memory simulator which models 3D-stacked memory within gem5. Also includes the workloads used for IMPICA (In-Memory PoInter Chasing Accelerator), an ICCD 2016 paper by Hsieh et al. at https://users.ece.cmu.edu/~omutlu/pub/in-memory-pointer-chasing-accelerator_iccd16.pdf
macsim
A heterogeneous architecture timing model simulator.
phoenix
an API and runtime environment for data processing with MapReduce for shared-memory multi-core & multiprocessor systems.
m1chaelyeung's Repositories
m1chaelyeung/2022-Machine-Learning-Specialization
m1chaelyeung/gem5
This is an read-only mirror of the gem5 simulator. The upstream repository is stored in https://gem5.googlesource.com, code reviews should be submitted to https://gem5-review.googlesource.com/. The mirrors are synchronized every 15 minutes.
m1chaelyeung/macsim
A heterogeneous architecture timing model simulator.
m1chaelyeung/ramulator-pim
A fast and flexible simulation infrastructure for exploring general-purpose processing-in-memory (PIM) architectures. Ramulator-PIM combines a widely-used simulator for out-of-order and in-order processors (ZSim) with Ramulator, a DRAM simulator with memory models for DDRx, LPDDRx, GDDRx, WIOx, HBMx, and HMCx. Ramulator is described in the IEEE CAL 2015 paper by Kim et al. at https://people.inf.ethz.ch/omutlu/pub/ramulator_dram_simulator-ieee-cal15.pdf Ramulator-PIM is used in the DAC 2019 paper by Singh et al. at https://people.inf.ethz.ch/omutlu/pub/NAPEL-near-memory-computing-performance-prediction-via-ML_dac19.pdf
m1chaelyeung/PIMSim
PIMSim is a Process-In-Memory Simulator with the compatibility of GEM5 full-system simulation.
m1chaelyeung/datastructs_and_algorithm
Data struct and algorithm introduction and implementation in C/C++/Java.
m1chaelyeung/book
m1chaelyeung/graphBIG
A Comprehensive Benchmark Suite for Graph Computing
m1chaelyeung/PIM_NDP_papers
m1chaelyeung/phoenix
an API and runtime environment for data processing with MapReduce for shared-memory multi-core & multiprocessor systems.
m1chaelyeung/GRIM
Source code of the processing-in-memory simulator used in the GRIM-Filter paper published at BMC Genomics in 2018: "GRIM-Filter: Fast Seed Location Filtering in DNA Read Mapping using Processing-in-Memory Technologies" (preliminary version at https://arxiv.org/pdf/1711.01177.pdf)
m1chaelyeung/IMPICA
This is a processing-in-memory simulator which models 3D-stacked memory within gem5. Also includes the workloads used for IMPICA (In-Memory PoInter Chasing Accelerator), an ICCD 2016 paper by Hsieh et al. at https://users.ece.cmu.edu/~omutlu/pub/in-memory-pointer-chasing-accelerator_iccd16.pdf
m1chaelyeung/HMC-MAC
Processing-in Memory Architecture for Multiply-Accumulate Operations with Hybrid Memory Cube