-
Machine Exercise 4 - Single Cycle MIPS Processor
- Go to this link for the online ME4 checker.
- Upload a zip file containing your RTL files only.
- The name for the zip file should be rtl.zip.
- The zip file should contain one directory named rtl which should contain all of your RTL files
- Inside that rtl directory, there should be a verilog file named single_cycle_mips.v
-
Machine Exercise 5 - Pipelined MIPS Processor
- Go to this link for the online ME5 checker.
- Upload a zip file containing your RTL files only.
- The name for the zip file should be rtl.zip.
- The zip file should contain one directory named rtl which should contain all of your RTL files
- Inside that rtl directory, there should be a verilog file named pipelined_mips.v