magetron/fpga-dns-adtm

Issues

• DRAM to save DNS msg

  #9 opened 4 years ago by magetron
  2

• fix VHDL test benches to use siphash

  #61 opened 4 years ago by magetron
  0

• report writeup tracker

  #64 opened 4 years ago by magetron
  3

• beautify README, prepare video and brush up on submission material

  #63 opened 4 years ago by magetron
  1

• Admin packet authentication

  #37 opened 4 years ago by magetron
  2

• enable rcode as generic constant in VHDL

  #62 opened 4 years ago by magetron
  0

• set dns reply option

  #58 opened 4 years ago by magetron
  0

• add script to set send dstMAC for FPGA

  #56 opened 4 years ago by magetron
  1

• update vhdl test suite to reflect on new admin packets, and various tests

  #43 opened 4 years ago by magetron
  0

• dstMAC filter not working properly

  #53 opened 4 years ago by magetron
  1

• decouple the modules, admin route and filter route

  #41 opened 4 years ago by magetron
  1

• hardware testbench via writing script of pkt-sender.out

  #39 opened 4 years ago by magetron
  4

• add feature to admin-builder, allow building admin config from config file

  #35 opened 4 years ago by magetron
  0

• add blocking stats counter, as well as reporting + admin server

  #33 opened 4 years ago by magetron
  0

• write packet receiver on the macOS NIC

  #47 opened 4 years ago by magetron
  1

• de-coupling the modules, to test seperately

  #40 opened 4 years ago by magetron
  1

• do DNS filtering

  #32 opened 4 years ago by magetron
  1

• Basic IP/UDP based ip / port filtering

  #10 opened 4 years ago by magetron
  8

• Bug observed of FIFO buffer size, need to test to confirm

  #27 opened 4 years ago by magetron
  7

• A Bug where changing contents are stale in FPGA

  #28 opened 4 years ago by magetron
  0

• Implement test bench

  #14 opened 4 years ago by magetron
  2

• Bug detecting Admin pkt, admin pkt needs to be sent multiples times for the board to detect

  #24 opened 4 years ago by magetron
  2

• Bug when receiving dst IP 192.168.88.88

  #23 opened 4 years ago by magetron
  7

• Improve FPGA sw prober

  #20 opened 4 years ago by magetron
  0

• FIFO bug fix

  #17 opened 4 years ago by magetron
  1

• FIFO buffer on TX and RX to speed up core clk

  #15 opened 4 years ago by magetron
  0

• IP/UDP Checksum generation on snd

  #8 opened 4 years ago by magetron
  1