manish-kj

manish-kj's Stars

• alexforencich/verilog-ethernet

  Verilog Ethernet components for FPGA implementation

  Language:Verilog2.2k677

• manish-kj/Posit-HDL-Arithmetic

  Universal number Posit HDL Arithmetic Architecture generator

  Language:Verilog5012

• manish-kj/PACoGen

  PACoGen: Posit Arithmetic Core Generator

  Language:Verilog6315