manishpatkar1996/ADPLL

The wireless communication industry has grown tremendously in the recent years, leading to strong demand for smaller, faster, better and less power consuming circuits. Digital circuits have better properties in these aspects, which have resulted in great interest for more digitally intensive circuits. Since frequency synthesis is an essential part of any wireless system, an All Digital PLL is very attractive. Phase Locked Loops are used in almost every communication system. Some of its uses include recovering clock from digital data signals, performing frequency, phase modulation and demodulation, recovering the carrier from satellite transmission signals and as a frequency synthesizer. All Digital PLLs (ADPLL) have low power consumption, small area, better noise immunity and better tolerance to bias drifts and PVT variations when compared to the Analog PLLs (APLL). They are more suitable for the monolithic implementation with other circuits compared to the traditional implementations of the PLLs. The All Digital PLLs are also independent of process variations and can be easily ported to di erent technologies. This project aims to create a model of All Digital Phase Locked Loop (ADPLL) with a reference frequency of 200kHz and implement using FPGA. The improvisations will be made as per the design requirements in VHDL in Xilinx. The simulation and test results of the ADPLL will also be presented to verify its operation .