Implementation of a single cycle MicroMIPs Microprocessor
- Implements basic fundamental structures of microprocesors which includes the following:
- Program Counter
- Control Unit
- Instruction Cache
- Data Cache
- Arithmic Logic Unit
- Next Address Block
- Register File
- Produces 21 Instructions (ADD, SUBTRACT, LOAD, JUMP, etc.)
- Uses a variety of basic building blocks such as multiplexers and demultiplexers for connection between components
- Implemented using VHDL and Quartus
- No hardware has been used yet
- Hasn't been tested on a FPGA board due to having too many pins
- Final design is implemented on a BDF file through Quartus