Micro Architecture at Santa Cruz (MASC)

UC Santa Cruz

Pinned Repositories

anubis
The ANUBIS benchmark suite for Incremental Synthesis
Language:C12 9 02
cmpe220fall16
Public repository of the UCSC CMPE220 class project
Language:Verilog10 19 61
docker-images
UCSC MASC dockerfiles to automate building ESESC, RISCV, LiveHD images
Language:Dockerfile6 7 30
esesc
ESESC: A Fast Multicore Simulator
Language:C134 32 1664
fluid
Fluid Pipelines
Language:Scala11 14 12
hdlagent
LLM Agent for Hardware Description Language
Language:Python11 19 16
hif
Hardware Interchange Format
Language:C++8 19 12
livehd
Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation
Language:FIRRTL206 29 17948
liveos
Liveos
Language:JavaScript7 6 12
MASC-AI-Synthesized-Cryptoprocessor
Language:Verilog6 4 00

Micro Architecture at Santa Cruz (MASC)'s Repositories

masc-ucsc/livehd
Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation
Language:FIRRTL206 29 17948
masc-ucsc/esesc
ESESC: A Fast Multicore Simulator
Language:C134 32 1664
masc-ucsc/hdlagent
LLM Agent for Hardware Description Language
Language:Python11 19 16
masc-ucsc/hif
Hardware Interchange Format
Language:C++8 19 12
masc-ucsc/MASC-AI-Synthesized-Cryptoprocessor
Language:Verilog6 4 00
masc-ucsc/pyrope_artifacts
Pyrope, a modern HDL with a Live flow
Language:C5 20 891
masc-ucsc/tree-sitter-pyrope
tree-sitter Pyrope grammar
Language:C4 19 11
masc-ucsc/desesc
Dromajo ESESC
Language:C++3 18 15
masc-ucsc/hdeval
Hardware Description Language Evaluation suite for LLM
Language:Python3 19 01
masc-ucsc/hhds
Hardware Hierarchical Dynamic Structures
Language:C++3 17 14
masc-ucsc/livehd_regression
LiveHD Regression suite and scripts
Language:Verilog3 20 00
masc-ucsc/mmm
Memory Marionette Model
Language:C++3 18 11
masc-ucsc/dromajo
RISC-V RV64GC emulator designed for RTL co-simulation
Language:C++1 2 02
masc-ucsc/superbp
Super Scalar Branch Predictor
Language:C++1 21 0
masc-ucsc/airspace-hugo
Airspace theme (Hugo version)
Language:CSS2 0
masc-ucsc/ariane
Ariane is a 6-stage RISC-V CPU capable of booting Linux
Language:SystemVerilog2 0
masc-ucsc/bazel_rules_hdl
Hardware Description Language (Verilog, VHDL, Chisel, nMigen, etc) with open tools (Yosys, Verilator, OpenROAD, etc) rules for Bazel (https://bazel.build)
Language:Starlark1 0
masc-ucsc/black-parrot
A Linux-capable RISC-V multicore for and by the world
Language:SystemVerilog1 0
masc-ucsc/black-parrot-sdk
Language:Python1 0
masc-ucsc/black-parrot-sim
Language:Dockerfile1 0
masc-ucsc/chipyard
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
Language:C1 0
masc-ucsc/docs
Documentation for LiveHD and Pyrope
Language:Ruby20 01
masc-ucsc/hlop
Hardware Logic Operation Library
Language:C++18 1
masc-ucsc/libelf
Fork from https://web.archive.org/web/20181111033959/www.mr511.de/software/libelf-0.8.13.tar.gz (needed by dromajo)
Language:C3 0
masc-ucsc/madaweb
HSC Website
Language:HTML26 01
masc-ucsc/OpenTimer
A High-performance Timing Analysis Tool for VLSI Systems
Language:Verilog1 0
masc-ucsc/riscv-boom
SonicBOOM: The Berkeley Out-of-Order Machine
Language:Scala1 0
masc-ucsc/slang
SystemVerilog compiler and language services
Language:C++1 0
masc-ucsc/termwave
Terminal Digital Electronics Wave viewer library
Language:C++20 0
masc-ucsc/tree-sitter-verilog
SystemVerilog grammar for tree-sitter