/impulse

Impulse is a retro-inspired FPGA music synthesizer, written in SystemVerilog using open-source tools.

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Impulse

Impulse is a retro-inspired FPGA music synthesiser with MIDI support, written in SystemVerilog. Think of it as the NES, SNES and Sega Genesis all combined together in one super awesome package.

Impulse is simulated, synthesized and iterated on using entirely open source tools: Icarus Verilog, Yosys, Nextpnr GTKWave and VSCode.

Directory layout:

  • build: Not included in Git, but this should be generated by CMake. It will contain the testbench compiled code, waveforms and Yosys synthesis output.
  • concept: Python code to test the overall concept of the synth (oscillators, mixing, etc).
  • docs: Contains documentation about the chip architecture.
  • rtl: SystemVerilog RTL code. The main source of Impulse.
  • scripts: Scripts for synthesis and simulation.
  • testbench: Scripts and SystemVerilog files that define testbenches for each module

Authors:

Project overview

About Impulse

TODO explain the synth here

Verification procedure

TODO explain, or link to document explaining, how we will verify it

Installing tools

This project relies on many open source tools for simulation and synthesis. You will need to compile all these tools from source, because they are either too outdated in the repositories, or not shipped at all.

Luckily for you, I've made a project called open_eda_builder which automatically produces bleeding-edge builds of these tools! To learn more and download a release, please visit: https://github.com/mattyoung101/open_eda_builder (this is completely free & open source, it doesn't cost any money to download).

If you don't want to use open_eda_builder, you could use Yosys' oss-cad-suite-build or build each of the tools listed in open_eda_builder from scratch.

Installing the remaining tools

There are a few tools that open_eda_builder does not ship, because the versions Ubuntu provides are actually suitable, or the tools are too general purpose (e.g. CMake).

These notes assume you are running an Ubuntu derivative, because I run Linux Mint. However, instructions should be relatively portable across Linuxes.

  • Install a recent version of CMake. I recommend using the CMake PPA
  • Install GTKWave: sudo apt install gtkwave
  • Install VSCode and the following additional components:
    • Verilog extension by Eirik PrestegĂĄrdshus
    • Install svls, the SystemVerilog language server: download from the GitHub repo and make sure the extracted binary is in VSCode's $PATH. I just moved it to /usr/local/bin.
    • Then, install the svls-vscode extension by dalance.
    • As you might be able to tell, this is all a bit of a hack, and not ideal (especially the fact that two extensions are required). I'm looking into whether or not I can create a better extension of my own design using Verible.

Congrats. You now have a full, 100% open source FPGA toolchain setup and installed.

Simulation

Introduction

The current simulation tool used is the bleeding-edge version of Icarus Verilog. This is an event driven simulator that mostly supports SystemVerilog, so is good for our use-case. Another simulator, Verilator, was also looked at - and might be used in future - but Icarus is easier to understand for me, for now.

Icarus Verilog (iverilog) works by transforming Verilog sources and testbenches into .vvp files, which is essentially bytecode for another program, vvp, which then performs the simulation. Both of these stages are handled automatically by the CMake script.

Running simulations

I use CMake as the build tool. It actually works surprisingly well for this, using custom targets. Here's how you can run the simulations:

  • cmake -B build to generate the build files
  • cd build
  • make ivl_sim to compile and execute SystemVerilog testbenches using Icarus Verilog

You can then look at the .vcd files in the build directory. They are in the FST file format, which is faster and better than all the others according to my reading. They can be viewed in GTKWave.

If you add or remove any SystemVerilog, you will need to run CMake due to the use of globs. Otherwise, between runs just type make sim in the build directory.

make clean will delete the VVP files. Currently VCD files are not deleted, but I'll do this in the future.

Note 1: In the near future I'd also like to support using Verilator and possibly Yosys CXXRTL as additional simulators, and compare the synth between them all to ensure correctness. In the mean time, I'll be sticking with Icarus though.

Note 2: I'd also like to support vunit or cocotb for verification.

Synthesis

Introduction

The main FPGA that the Impulse aims to be synthesized for is the Lattice ECP5. Specifically, we will either target the OrangeCrab or the ULX3S (probably the latter because of its built-in audio jack). Eventually, we will also target synthesis on our custom PCB, but that is for the future.

As stated previously I'm currently using Yosys/Nextpnr. In the future, I may also look into Verilog to Routing and compare these two tools' performance.

Synthesizing for the Lattice ECP5

TODO

Synthesizing for ASIC

Right now we do not have the financial resources to target ASIC production (both in terms of EDA tools and actually getting on a shuttle), and it is unlikely that this design would be good enough to fab anyway.

That being said, given I am very interested in ASIC fabrication, once this project is complete and tested on an FPGA, I plan to look into OpenLane and the Skywater 130nm open-source PDK to see if I can produce a design that could in theory be fabbed, just for fun!

Licence

Mozilla Public License 2.0