maximGt/ICContest-2018-Preliminary-HuffmanCoding

2018 IC Design Contest Preliminary - Huffman Coding

Directory Tree - Main Folder & Files

run_nc.sh -- Run function simulation
run_nc_post.sh -- Run timing simulation
dc -- Design Compiler Relate

.synopsys_dc.setup -- Set Design Compiler's parameter
DC_syn.tcl -- Script for Design Compiler
huffman.sdc -- Constraint file
huffman_syn.v -- Netlist from Design Compiler

doc -- Related documents

B_ICC2018_priliminary_grad_cell_based.pdf -- Problem Description

sim --Ncverilog Relate

pre_sim.f -- Script for function simulation
post_sim.f -- Script for timing simulation
pattern1.dat -- Test data 1
pattern2.dat --Test data 2
pattern3.dat --Test data 3
golden1.dat -- Answer data 1
golden2.dat -- Answer data 2
golden3.dat -- Answer data 3

src -- Source code

huffman.v -- Main module
tb.v -- Testfixture

Finite State Machine

FSM in huffman.v line:141~178

AUTHORS

Yu-Cheng Chou