mayyxeng

CS PhD student at EPFL.

EPFLSwitzerland

Pinned Repositories

parendi
Parendi: Thousand-way Parallel RTL Simulation on the Graphcore IPU
Language:C++13 1 01
parendi-paperspace-demo
Parendi's demo on Paperspace IPUs
Language:SystemVerilog0 1 00
manticore-compiler
Language:Scala3 1 10
manticore-hw
Language:Scala3 1 00
BLIFMaker
A dot to BLIF converter
Language:C++00
BSMAKER
Virtual Bit-Stream Maker
Language:C++00
cs550-ct-verif
A fork of ct-verif
Language:Makefile10
kitty
C++ truth table library
Language:C++1 0 00
streamblocks-partitioning
Partitioning
Language:Java1 1 01
streamblocks-platforms
StreamBlocks available platforms
Language:C++5 3 13

mayyxeng's Repositories

mayyxeng/cs550-ct-verif
A fork of ct-verif
Language:Makefile10
mayyxeng/kitty
C++ truth table library
Language:C++1 0 00
mayyxeng/BLIFMaker
A dot to BLIF converter
Language:C++00
mayyxeng/BSMAKER
Virtual Bit-Stream Maker
Language:C++00
mayyxeng/COM-503
Homework repository for COM-503 (Performance Evaluation) at EPFL
Language:TeX
mayyxeng/constellation
A Chisel RTL generator for network-on-chip interconnects
mayyxeng/cs-550
EPFL's Formal Verification in Fall 2021
Language:TeX3 0
mayyxeng/cs550-dudect
A modified version of DudeCT
Language:C
mayyxeng/cva6-synth-sim
A fork of cva6 with a "synthesizable" testbench for verilator
Language:SystemVerilog
mayyxeng/overlay_builder
Language:Scala
mayyxeng/streamblocks_jenkins
streamblocks remote build with jenkins
Language:Python
mayyxeng/turnus
The core repository of TURNUS: a design space exploration and optimization framework for dynamic dataflow programs