This is an archived project from Purdue's ECE437 computer architecture course. The included source is an implementation of a cached, pipelined dual-core MIPS instruction set processor.
The project is not setup to work as is. The included code source is only the bare bones vhdl and is intended for reference only. The assembly programs included in the folder were run on the cpu and the output of the execution is included in the form of hex dumps (pretty unreadable).
It seems it might be a simple project to port this to an open source logic simulator (this project was built with modelsim).