Introduction
| Discipline | Computer Science and Engineering |
|---|---|
| Lab | CS203- Design of Digital System Lab |
| Experiment | SA0 and SA1 fault on a half adder circuit |
About the Experiment
Detection of both SA0 and SA1 faults on a Half Adder circuit implemented by AND and XOR gates.
| Name of Developer | Dr. Biswajit R Bhowmik |
|---|---|
| Institute | National Institute of Technology Karnataka, Surathkal |
| Email id | brb@nitk.edu.in |
| Department | Computer Science and Engineering |
Contributors List
| SrNo | Name | Student | Department | Institute | Email id |
|---|---|---|---|---|---|
| 1 | Chirag R | B.Tech | CSE | NITK Surathkal | chiragr.201ec114@nitk.edu.in |
| 2 | Md Rakib Hasan | B.Tech | CSE | NITK Surathkal | rakib.201cs132@nitk.edu.in |
| 3 | Attada Ramprasad | B.Tech | CSE | NITK Surathkal | attadaramprasad.201cs210@nitk.edu.in |
| 4 | Hari Chetan Kurapati | B.Tech | CSE | NITK Surathkal | harikurapati.201cs119@nitk.edu.in |
| 5 | Aniketh Narayan Bellala | B.Tech | CSE | NITK Surathkal | aniketh.201cs108@nitk.edu.in |