This project is an 8-bit discrete CPU based on original SAP-1 architecture and mainly inspired by Ben Eater's implementation of it. The main differences in this design are as follows:
- 8-bit Porgram Counter.
- 256 bytes of RAM.
- 12-bit Instructions Register.
- Latching mechanism for Instructions Register to enable reusing the Fetch flow in MSAP-1 uCodes.
- Enabling automated RAM input for programming
- Using Schmitt Trigger Inverters instead of SR Latches for clock module switch debouncing, that was creating some issues in certain situations.
- Lower power consumption achieved by using CMOS chips instead of Low-Power Schottky, higher efficiency LEDs as well as using lower chip count in total, enabled by different debouncing circuit and non-inverting RAM. (<300 mA including the programmer and all LEDs on)
- Better noise management, allowing faster clock speeds.
MSAP-2 will include:
- MMU to enable RAM segmentation and support for up to 2KB of RAM
- More control signals by multiplexing the signals that are never enabled together
- Better ALU, supporting more operations
- Interrupt support
- Stack support
There are a few sample programs written in MSAP-1 assembly that can be found here. At the moment, the example programs are as follows:
- Bounce : indefinitely adds 1 to a base of 0 until it reaches 255 and then subtracts 1 until it reaches 0
- Division : divides two 8 bit integers
- Multiplication: multiplies two 8 bit integers
- Fibonacci: calculates Fibonacci series
- SquareRoot: calculates the square root of a given 8 bit integer
- NthRoot: calculates the nth root of a given 8 bit integer
- Factorial: calculates the factorial of a given 8 bit integer
You can use CPU Debugger project for this purpose.
Main oscillator of the clock module is an LM555 chip and it can be controlled with R1 potentiometer. The clock module contains two switches to enable bi-stable and mono-stable modes. The switches are debounced via 100K-10nF RC circuit connected to an input of U2, which is an Inverting Schmitt Trigger, providing better noise control over the clock signal in faster clock speeds due to a possible higher mean time between bounces for mono-stable switch (SW2) for synchronously coupled chips, such as cascaded CMOS binary counters that rely on clean, corectly timed inputs. Failure to correctly debounce this switch causes all sorts of unpredictable behaviors.
This module contains two cascaded 4-bit, presettable binary counters (74HC161), creating an 8-bit binary counter.
These are two 8-bit registers, each created with two 4 bit D flip-flops (74HC173).
This module contains two 4-bit full adders (74LS283) and two quad XORs (74HC86) to create 2's complement of second operand (coming from B register) to enable subtraction. This means that this module can add and subtract two 8-bit numbers.
This module contains two 4-bit register for the memory address, an HM6116P 2KB S-RAM with non-inverting I/O and circuitry for multiplexing data and address input from either the bus or the programmer. There are two discrete transistors in this module. Q1 is an NPN BJT transistor creating a buffer circuit to minimize the clock signal distortion caused by the RC circuit that is used for creating a pulse signal to synchronize RAM input. Q2 is a P-channel MOSFET used to disconnect power from the RAM input multiplexers to avoid them sinking current from RAM I/O pins, because 74LS/HC157 doesn't have a high impedence mode. Note that since I wanted to avoid using a MSOFET for each I/O pin, this circuit only works if U42 and U43 are Low-Power Schottky series and not CMOS, since CMOS chips will still be powered via their ESD protection diodes on their pins.
This module also contains a switch that allows selection between program or run mode. In the program mode, the RAM input is connected to the CPU programmer interface and in the run mode, it's connected to the bus. There are two output signals here that are used by the programmer. One is the active-low MNW signal (Manual Write) and the other is active-high PM signal (Program Mode)
This module contains a 4-bit register for OpCode and an 8-bit register for Operand. It works in such a way that it toggles between OpCode and Operand registers every time the II control signal is enabled and only enables the OpCode register output after a fetch cycle is done, until the next time that asynchronous RST signal is enabled. The toggle mechanism is achieved by a 4 bit presettable counter and a demultiplexer which keeps the IE pins high in between. The latching mechanism is achieved by a JK flip-flop that enables reusing fetch operation in uCodes. The input signal T0 which is active-low, is connected to the Control Logic's u-instruction step decoder chip, indicating step 0. This signal resets the toggle mechanism by resetting the 4-bit counter.
This module contains a u-instruction step counter, created by a 4-bit counter and a 3 to 8 line demultiplexer which is connected to two 2Kx8-bit AT28C16 EEPROMs that contains the uCodes and two quad inverters to create the active-low signals. This is to keep the output of EEPROMs always active-high, regardless of the control signal.
This module contains an 8 bit register to store the output value, a 555 timer that with a dual JK flip-flp and a decoder, form a multiplexer for 4 seven segment displays. an AT28C16 EEPROM is used to store Binary to 7-segment decoding logic. It also contains a switch (SW3) which allows switching between signed and unsigned presentation of the output.
This module contains a 4 bit D flip-flop to keep flags that can be used for conditional jumps in u-instructions and circuitry to check for zero sum out from ALU. currently it keeps carry flag (CF) and zero flag (ZF). The output of the register is connected to address lines of control logic EEPROMs, so the instructions executed for JC and JZ OpCodes changes.
This is a simple circuitry to rest all the modules by generating both active-low and active-high signals that are required to asynchronously reset the flip-flops and counters. It also used to generate the active-low, RSTSTP signal that is used to reset the u-instruction step counter as well as resetting the JK flip-flop that is used for latching the OpCodes in instructions register.
