/MeowV64

A superscalar RISC-V CPU with out-of-order execution and multi-core support

Primary LanguageScalaMIT LicenseMIT

MeowV64

MeowV64 is a synthesizable and configurable superscalar RISC-V CPU with out-of-order execution, L1/L2 caches and multicore support. MeowV64 implements the RV64IMAFDCSU ISA.

Authors

See AUTHORS file

License

All code under this repository is released under the MIT license. See LICENSE file.