A seminar paper about hardware caches and how to use them effectively.
- A summary which I wrote for my website can be found here.
- You can download the paper here.
- Slides created with org-reveal for an accompanying presentation are available here (hit Space or N to move to the next slide).
Typical present-day CPUs have two or more levels of caches. This article provides basic insight into their operation and presents key architectural properties which suggest possible program optimizations. The abstract external memory model (EMM) for memory hierarchies and the cache-oblivious model (COM) derived from it are presented briefly.