/RISC-V-Single-Cycle-Logisim

This repository contains the implementation of the RISC-V Single Cycle Core on Logisim

RISC-V-Single-Cycle-Logisim

This repository contains the implementation of the RISC-V Single Cycle Core on Logisim by the 12 students team.
They have created the single cycle core according to the RISC-V ISA and simulated their programs written on the RISC-V Assembly and verified the working of their datapath.
This team includes:

  1. M. Mohsin Raza 18B-015-SE
  2. Talha Ahmed 18B-024-SE
  3. Ubab Nadeem 18B-130-SE
  4. Fizza Jaffery 18B-133-SE
  5. Almas Ibrahim 18B-088-SE
  6. Raheel Siddiqui 18B-010-SE
  7. Farooq Hidayat 18B-122-SE
  8. M. Shahzaib 18B-016-SE
  9. Shahzaib Kashif 18B-050-SE
  10. Waleed Sohail 18B-123-SE
  11. M. Monis 18B-036-SE
  12. M. Mohsin Siddiqui 18B-023-SE