meyanik

Pinned Repositories

litex
Build your hardware, easily!
Language:C2.9k 97 802550
GITT_Start
00
KWS-ASIC
Keyword Spotting Accelerator chip design for Efabless AI-design-contest
Language:Verilog00
Lab_Gunlukleri
GITT ve GATE takımları için lab günlükleri
0 2 00
Lambda-Shortlane
Just a simple script for openlane and Tang-Nano FPGA
Language:Shell20
LM-RISCV-DV
An Open-Source Design and Verification Environment for RISC-V
Language:SystemVerilog00
My_LiteX_playground
My LiteX playground
Language:Python0 1 00
salihe
Language:Coq00
TCL_Dersleri
TCL öğrenmek isteyenler için küçük örnekler serisi
Language:Tcl10
ascon-verilog
Verilog Hardware Design of Ascon v1.2
Language:SystemVerilog19 1 24

meyanik's Repositories

meyanik/Lambda-Shortlane
Just a simple script for openlane and Tang-Nano FPGA
Language:Shell20
meyanik/TCL_Dersleri
TCL öğrenmek isteyenler için küçük örnekler serisi
Language:Tcl10
meyanik/GITT_Start
00
meyanik/KWS-ASIC
Keyword Spotting Accelerator chip design for Efabless AI-design-contest
Language:Verilog00
meyanik/Lab_Gunlukleri
GITT ve GATE takımları için lab günlükleri
0 2 00
meyanik/LM-RISCV-DV
An Open-Source Design and Verification Environment for RISC-V
Language:SystemVerilog00
meyanik/My_LiteX_playground
My LiteX playground
Language:Python0 1 00
meyanik/salihe
Language:Coq00