- Add Sources -> Add or create design sources -> Define Verilog Modules
- Create Block Design -> Add IP and Add Module (our custom verilog modules)
- Generate output Products of the Block design A Vivado IP instance allows you to generate various output products (instantiation template, synthesis, simulation, example designs, etc.) on demand. Some products are generated by default.
- Create HDL Wrapper on the Block design to generate the external IO pins for Synthesis & Implementation
- Optional: Write Testbench code in Verilog by Add Sources->Create simulation sources.Then Run simulation
- Run Synthesis
- Run Implementation
- Generate Bitstream
- File->Export->Export Hardware (Include Bitstream)
- Launch SDK
- New->Application Project->Empty Application
- New->Board Support Package system.mss -> Import Examples for various Peripheral Devices system.hdf -> Describes the memory mapped addresses
- Project->BuildConfigurations->SetActive->Debug or Release
- Run>DebugConfigurations->LaunchOnHardware
- Run->RunConfigurations
- Optional->SDK Terminal-> + (ConnectToSerialPort) BaudRate:115200, DataBits:8, StopBits:1, Parity:None, FlowControl:None 0indexed Port1 for ZyboZ7
Vivado->Write Project Tcl. WindowsExplorer->Copy srcs, sdk folders
- PL Fabric Clocks not working or updating - The Clocks are configuration of the Zynq PS.
The bitstream only modifies the PL fabric (fpga). So we will have to generate FSBL to configure the PS. - Unspecified I/O Standard: 2 out of 132 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value.
Use LVCMOS33 as IOSTANDARD and select the pins before generating the bitstream. - We see the module's IO ports requested in the constraints file when generating bitstream
Create HDL Wrapper on the high level Block design