/keyv

RISC-V processors implemented using the asynchronous KeyRing microarchitecture

Primary LanguageVHDLOtherNOASSERTION

KeyV : In-order /KeyRing/ self-timed processors based on the RISC-V ISA

This project explores the design trade-offs of the KeyRing asynchronous microarchitecture. It is used to design KeyV, an in-order KeyRing processor based on the RV32IM user-level RISC-V ISA specification, implemented using the TSMC65GP (65nm) ASIC technology. KeyV is compared with SynV, a 6-stages pipeline synchronous clock-gated processor implementing the same ISA and targeting a similar design flow with the same ASIC technology.

Setup

  • This project relies on CAD tools and technologies provided by CMC. It was developed under Centos 7, and it is expected to work (without major modifications) in any CMC environment, including a virtual machine instance accessibe via the NDN Cloud.

  • Setting-up the environment must be performed prior to doing any work on this project. To do so, execute the setup.csh script from the root of the project in a tcsh shell:

    source setup.csh

Software

  • Programs are compiled for the processors using the dedicated Makefile in the software directory. The help is self-explanatory:

    make help

  • The RISC-V toolchain used in this project is deployed in the toolchain directory, using the build_toolchain_.csh script.

  • The project includes a (simplified) custom firmware, which handles basic memory operations.

    • crt.S: Assembly program which handles basic starting & ending functions (reset, call main, traps…)
    • stdlib.c: C program which handles basic memory operations (malloc) & printing functions (write in a scratchpad memory)
    • link.ld: Linker script which reflects the core memory organization in the software.

  • Different benchmarks are available in the benchmark folder to validate the behaviour of the processor, and evaluate its performances:

    • basic: Simple assembly program adapted to test each instructions in the ISA.
    • fibo: Simple C program running few iterations of the fibonacci algorithm. It is used to test the toolchain with the custom firmware functions.
    • dhrystone: The Dhrystone benchmark adapted to use the custom firmware. It is used to evaluate the performances of the processor.
    • coremark: The Coremark benchmark adapted to use the custom firmware. It is used to evaluate the performances of the processor.

Simulation

  • The simulation is performed with Modelsim, and is handled by the Makefile in the simulation directory. The help is self-explanatory:

    make help

  • Simulation flows rely on the following Tcl scripts:

  • Post-synthesis simulations rely on SDF files that must first be produced by DC or PrimeTime.

  • SAIF files are generated to evaluate the dynamic power consumption of the design in DC.

Synthesis

  • The synthesis flow is handled by the Makeifle in the synthesis directory. The help is self-explanatory:

    make help

  • Synthesis flow relies on the following scripts:

  • Timing constraints for the SynV / KeyV processors are respectively written in:

  • Clock gating for SynV is handled separately: -cg.tcl

  • SDF files are produced by PrimeTime:

  • Power analysis is performed by DC based on post synthesis acitvity recorded in SAIF

Results