/trainVHDL

Primary LanguageVHDL

VHDL TRAINING EXERCICE

in this repo u will finde somme exercice with solution for VHDL, exercice like MUX FLIP FLOP..

Example

  git clone https://github.com/misarb/trainVHDL/tree/main/exercice/buildCircuit

Contributing

Contributions are always welcome!

To do

[ ] more exercice :).

Clone this project

  git clone https://github.com/misarb/trainVHDL.git

CD into the project

  cd trainVHDL

Download dependencies

1- for windows you can use Quartes Or modelSim to simulit the result
1- for linux u can use ModelSim or GHDL to analyse and gtkwave to simulate the result of your VHDL CODE

Run the project

 in directory ther's a file called `testVhdlCode` use commandLine if you are in linux if you are in windows just use ModelSim directly will do the reset

Authors