Pinned Repositories
776final
casperfpga
Software control for CASPER FPGAs
DailyFramework
device-tree-xlnx
Linux device tree generator for the Xilinx SDK (Vivado > 2014.1)
flag_gpu
CPU/GPU codes for real-time beamforming and correlations for the Focal L-Band Array for the GBT (FLAG) phased-array feed. To be used with the hashpipe thread management system.
grating
Grating is a GPU-based polyphase filter bank (PFB) spectrometer.
hashpipe
High Availability Shared Pipeline Engine
katcp
oversampled-pfb
rfdc-snapshot
mitchburnett's Repositories
mitchburnett/oversampled-pfb
mitchburnett/776final
mitchburnett/casperfpga
Software control for CASPER FPGAs
mitchburnett/rfdc-snapshot
mitchburnett/DailyFramework
mitchburnett/device-tree-xlnx
Linux device tree generator for the Xilinx SDK (Vivado > 2014.1)
mitchburnett/flag_gpu
CPU/GPU codes for real-time beamforming and correlations for the Focal L-Band Array for the GBT (FLAG) phased-array feed. To be used with the hashpipe thread management system.
mitchburnett/grating
Grating is a GPU-based polyphase filter bank (PFB) spectrometer.
mitchburnett/hashpipe
High Availability Shared Pipeline Engine
mitchburnett/katcp
mitchburnett/kutleng_skarab2_bsp_firmware
The vivado firmware for the skarab2
mitchburnett/MATLAB_PV_LIB
MATLAB PV function library
mitchburnett/meson
The Meson Build System
mitchburnett/mkid-readout-firmware
RFSoC MKID Readout Firmware
mitchburnett/mlib_devel
mitchburnett/mm
Decompilation of The Legend of Zelda: Majora's Mask
mitchburnett/pisces
Pisces: A practical seismological database library in Python.
mitchburnett/pvlib-python
A set of documented functions for simulating the performance of photovoltaic energy systems.
mitchburnett/ras-devel
BYU Radio Astronomy Systems group developer
mitchburnett/rdmagpu
mitchburnett/statsmodels
Statsmodels: statistical modeling and econometrics in Python
mitchburnett/tutorials_devel
Tutorials available here:
mitchburnett/xGPU
A GPU based FX correlator for radio astronomy
mitchburnett/xml2vhdl
Python code to generate AXI4Lite VHDL register interfaces and Interconnect from a XML memory map specification.