mnentwig/verilogSnippets

collection of Verilog code samples e.g. for FPGA

verilogSnippets

collection of Verilog code samples e.g. for FPGA

asynchronous FIFO with valid/ready protocol

testbench with PN data source

axiToReadyValid

AXI-lite slave with four ready-/valid ports

axiMaster

AXI-lite master (largely for simulation)

workflow

• makefile for MinGW
• .bat file for mapping directory to f: drive on windows (ugly but efficient approach to managing path names)