Pinned Repositories
aib-phy-hardware
Android-ImageMagick7
Fully featured, latest builds of imagemagick 7 (7.0.9-17) for Android. Featuring a full build of very many libraries (delegates)
C4-PlantUML
C4-PlantUML combines the benefits of PlantUML and the C4 model for providing a simple way of describing and communicate software architectures
covid19_inference_forecast
dpll
A collection of phase locked loop (PLL) related projects
drawio-desktop
Official electron build of diagrams.net
e200_opensource
The Ultra-Low Power RISC Core
eda-collection
edalize
An abstraction library for interfacing EDA tools
FPGA-peripherals
:seedling: :snowflake: Collection of open-source peripherals in Verilog
mohamadahmad's Repositories
mohamadahmad/covid19_inference_forecast
mohamadahmad/dpll
A collection of phase locked loop (PLL) related projects
mohamadahmad/aib-phy-hardware
mohamadahmad/Android-ImageMagick7
Fully featured, latest builds of imagemagick 7 (7.0.9-17) for Android. Featuring a full build of very many libraries (delegates)
mohamadahmad/C4-PlantUML
C4-PlantUML combines the benefits of PlantUML and the C4 model for providing a simple way of describing and communicate software architectures
mohamadahmad/drawio-desktop
Official electron build of diagrams.net
mohamadahmad/e200_opensource
The Ultra-Low Power RISC Core
mohamadahmad/eda-collection
mohamadahmad/edalize
An abstraction library for interfacing EDA tools
mohamadahmad/FPGA-peripherals
:seedling: :snowflake: Collection of open-source peripherals in Verilog
mohamadahmad/ghdl
VHDL 2008/93/87 simulator
mohamadahmad/hdl4fpga
VHDL library 4 FPGAs
mohamadahmad/icestudio
:snowflake: Visual editor for open FPGA boards
mohamadahmad/linux-nvme
NVME patches for (ARCH) linux
mohamadahmad/myhdl
The MyHDL development repository
mohamadahmad/ppk-nrf91
How to use Nordic Power profiling kit with nRF91 DK
mohamadahmad/RapidWright
Build Customized FPGA Implementations for Vivado
mohamadahmad/Ripes
A graphical processor simulator and assembly editor for the RISC-V ISA
mohamadahmad/riscv-dv
SV/UVM based instruction generator for RISC-V processor verification
mohamadahmad/riscv-ovpsim
OVP Simulator for RISC-V
mohamadahmad/RISCV_CPU
A FPGA supported RISC-V CPU with 5-stage pipeline implemented in Verilog HDL