mongrelgem

Aspiring Hardware Engineer

Pinned Repositories

Chatbot-2.0
A Recurrent Sequence to Sequence, multi-domain generative conversational model chatbot implemented in pytorch
Language:Python2 3 00
cMIPS
A complete classic 5-stage pipeline MIPS 32-bit processor, including a 2-bit branch predictor, a branch prediction buffer and a direct-mapped cache.
Language:Verilog5 1 00
RISCY
Simple RISC-V RV32I CPU in VHDL for use in FPGA Designs
Language:VHDL11 2 04
UART-RTL-Physical-Design
Complete ASIC Design of UART Interface with Baud Rate Selection :- RTL to GDS2
Language:Perl4 2 03
Verilog-Adders
Implementing Different Adder Structures in Verilog
Language:Verilog60 2 016
Verilog-I2C-Interface-Modules
Modular Verilog I2C Interface Components for Rapid Prototyping in FPGAs with MyHDL Testbench
0 1 00
Verilog-PCIexpress-Components
Modular Verilog PCIexpress Interface Components with complete MyHDL Testbench for FPGA deployment
10 0 01

mongrelgem/Verilog-Adders
Implementing Different Adder Structures in Verilog
Language:Verilog60 2 016
mongrelgem/RISCY
Simple RISC-V RV32I CPU in VHDL for use in FPGA Designs
Language:VHDL11 2 04
mongrelgem/Verilog-PCIexpress-Components
Modular Verilog PCIexpress Interface Components with complete MyHDL Testbench for FPGA deployment
10 0 01
mongrelgem/cMIPS
A complete classic 5-stage pipeline MIPS 32-bit processor, including a 2-bit branch predictor, a branch prediction buffer and a direct-mapped cache.
Language:Verilog5 1 00
mongrelgem/UART-RTL-Physical-Design
Complete ASIC Design of UART Interface with Baud Rate Selection :- RTL to GDS2
Language:Perl4 2 03
mongrelgem/Chatbot-2.0
A Recurrent Sequence to Sequence, multi-domain generative conversational model chatbot implemented in pytorch
Language:Python2 3 00
mongrelgem/Verilog-I2C-Interface-Modules
Modular Verilog I2C Interface Components for Rapid Prototyping in FPGAs with MyHDL Testbench
0 1 00