Early experiments with writing FPGA code in systemverilog.
An early attempt at building up a risc-type cpu. This is currently at a very early stage and not at all usable.
Code implemented based on a youtube series attempting to build a microcode cpu for playing Zork. Unfortunately the project didn't finish so this is incomplete. However I learned about writing C++ unit tests for functional verification.
Using Intel's Quartus Prime lite IDE for writing systemverilog for the DE10-lite FPGA demo board from terasic.