mostafa0001-me

Pinned Repositories

Piplined-RiscV-Processor
Language:Verilog10
Bitnine-Coding-Test
Answers to the first two questions in the Bitnine coding test
Language:C00
course-JS-and-the-DOM
Language:JavaScript00
darsh
00
Distributed-Systems
Course Project
00
doctor
login and sign up linked with firebase
Language:Dart00
noteSauce
My Notes for the \st{useless} college
Language:TeX00
RCA---Hardware-Modeling
Schematic and hardware layout of a ripple carry adder using tanner software
00
RISC-v-Processor-demo
A working processor that applies the concepts proposed in the RISC-V philosophy that works on (ADD, SUB, BEQ, LW, SW, OR, AND).
Language:Verilog00
RISCV-Processor
Language:Verilog00

mostafa0001-me's Repositories

mostafa0001-me/Distributed-Systems
Course Project
mostafa0001-me/RCA---Hardware-Modeling
Schematic and hardware layout of a ripple carry adder using tanner software
mostafa0001-me/Travel_Reservation_System
Flights and hotels reservation system simulation using C++
Language:C++
mostafa0001-me/Piplined-RiscV-Processor
Language:Verilog1
mostafa0001-me/Bitnine-Coding-Test
Answers to the first two questions in the Bitnine coding test
Language:C
mostafa0001-me/ytopp1
An extensible TUI system monitor written in Rust
Language:Rust
mostafa0001-me/RISCV-Processor
Language:Verilog
mostafa0001-me/RISC-v-Processor-demo
A working processor that applies the concepts proposed in the RISC-V philosophy that works on (ADD, SUB, BEQ, LW, SW, OR, AND).
Language:Verilog
mostafa0001-me/course-JS-and-the-DOM
mostafa0001-me/noteSauce
My Notes for the \st{useless} college
Language:TeX
mostafa0001-me/doctor
login and sign up linked with firebase
mostafa0001-me/darsh