Pinned Repositories
ara
The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core
cheshire_fork
A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
core-v-polara-apu
The OpenPiton Platform
coremark
CoreMark® is an industry-standard benchmark that measures the performance of central processing units (CPU) and embedded microcrontrollers (MCU).
cv32e40p
CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
cva6
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
dummy_vip
Files for the IP Integration Exercise
fpnew
Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
halutmatmul
Hashed Lookup Table based Matrix Multiplication (halutmatmul) built on MADDness/bolt
RV-MAGIC
mp-17's Repositories
mp-17/RV-MAGIC
mp-17/ara
The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core
mp-17/cheshire_fork
A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
mp-17/core-v-polara-apu
The OpenPiton Platform
mp-17/coremark
CoreMark® is an industry-standard benchmark that measures the performance of central processing units (CPU) and embedded microcrontrollers (MCU).
mp-17/cv32e40p
CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
mp-17/cva6
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
mp-17/dummy_vip
Files for the IP Integration Exercise
mp-17/fpnew
Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
mp-17/halutmatmul
Hashed Lookup Table based Matrix Multiplication (halutmatmul) built on MADDness/bolt
mp-17/llvm-project
mp-17/picolibc
picolibc (formerly newlib-nano)
mp-17/project-updates
mp-17/pulp-runtime
Simple runtime for Pulp platforms
mp-17/pulp_soc
mp-17/riscv-code-size-reduction
mp-17/riscv-opcodes
RISC-V Opcodes
mp-17/riscv-vectorized-benchmark-suite
RiVEC Bencmark Suite
mp-17/snitch_cluster
An energy-efficient RISC-V floating-point compute cluster.
mp-17/tutoring_hkn
Repository to store and work on the material related to tutoring