/hardware-accelerated-hog-svm

HOG-SVM algorithm implemented in a Zynq 7000 SoC (Digilent ZYBO)

hardware-accelerated-hog-svm

An implementation of the Histogram of Oriented Gradients algorithm, along with Support Vector Machine classification model.
Created for our undergraduate thesis project dealing with dynamic traffic management based on embedded hardware-accelerated vehicle detection with SUMo and Unity simulations.

Results

The FPGA hardware acceleration achieves a 13x speedup compared to the software Raspberry Pi implementation. While this does result in decreased robustness (decrease in F1/MCC scores), the throughput increase in the resulting dynamic traffic managment simulation is still maintained.

Details

Implemented using the ff:

datasets

Contains the datasets used for training and testing. Increasing sampled dataset as of May 17, 2018.

hog_svm_fpga

The hardware implementation of the HOG-SVM algorithm, done in HLS C++. Vivado HLS WebPACK 2018.1 project. The integrated Xillybus IP core is also included, in a Vivado project folder.

interface

The software wrapper for the Zybo, along with interaction with the rest of the traffic management network

opencv_benchmark

Implementation, training, and testing of the HOG-SVM algorithm for deskops. Visual Studio 2017 solution.

benchmark

Benchmarking of the hardware implementation of the HOG-SVM algorithm. Includes benchmarking for RasPi embedded systems

results

Results collated so far, along with the draft of the overall thesis project.

Step by Step Guide

  1. Install Vivado HLS. The WebPACK edition is fine, if you're using boards like the Zybo.
  2. Install Xillinux for the Zynq Zybo, or the Zynq board of your choice. If not using a Zynq board, refer to the Xillybus Documentation for information on the specific board.
  3. Compile OpenCV 3.4.1 for both the PC and the Zynq board. CUDA support is optional for the PC, but very helpful when trying out different features. If using Windows, also install Visual Studio the benchmark tools are in a Visual Studio solution. Read the Windows or Linux compile instructions.
  4. Follow the co-processing guide for generating the bitstream. The Vivado HLS project folder and the Xillybus Vivado project folder is already included in the project.
  5. Load the custom bitstream to the Zynq board.
  6. Compile the interface program. Use the Makefile provided. Note that it uses the C++ 2014 standard.
  7. Run the interface program to connect with the rest of the program.