Pinned Repositories
alpha-release
Builds, flow and designs for the alpha release
command-line-tutorial
infufrgs
Latex templates for documents of INF/UFRGS
ioPlacer
IO and Pin Placer for Floorplan-Placement Subflow
oh
Silicon proven Verilog library for IC and FPGA designers
OpenROAD
OpenROAD's unified application implementing an RTL-to-GDS Flow
z3
The Z3 Theorem Prover
rsyn
rsyn-x
Rsyn – An Extensible Physical Synthesis Framework
TritonCTS
Source codes and calibration scripts for clock tree synthesis
mpfogaca's Repositories
mpfogaca/alpha-release
Builds, flow and designs for the alpha release
mpfogaca/command-line-tutorial
mpfogaca/infufrgs
Latex templates for documents of INF/UFRGS
mpfogaca/ioPlacer
IO and Pin Placer for Floorplan-Placement Subflow
mpfogaca/oh
Silicon proven Verilog library for IC and FPGA designers
mpfogaca/OpenROAD
OpenROAD's unified application implementing an RTL-to-GDS Flow
mpfogaca/z3
The Z3 Theorem Prover
mpfogaca/OpenROAD-flow
OpenROAD's top level repo pointing to stable binaries, code, sample designs and an example flow
mpfogaca/RePlAce
RePlAce global placement tool
mpfogaca/rsyn-x
Rsyn – An Extensible Physical Synthesis Framework