/Analog-Design-of-Clock-Distribution-Network-using-Standing-Waves

This project studies the idea of a standing wave-based clock distribution network. This report demonstrates the thought process & testbenches used to explore this concept for a 10 GHz clock input.

Analog Design of Clock Distribution Network using Standing-Waves

This project studies the idea of a standing wave-based clock distribution network. This report demonstrates the thought process & testbenches used to explore this concept for a 10 GHz clock input.

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Design Implementation:

Design1
Design2
Design3

* Waveforms:

WV1
WV2
WV3
WV4

* Results:

WV5
WV6

Key References:

[1] G. Li, W. Lee, D. Cui, B. Zhang, A. Momtaz and J. Cao, "Standing wave based clock distribution technique with application to a 10 × 11 Gbps transceiver in 28 nm CMOS," 2015 IEEE Asian Solid-State Circuits Conference (A-SSCC), Xiamen, China, 2015.

[2] J. Poulton et al., "A 14-mW 6.25-Gb/s Transceiver in 90-nm CMOS," in IEEE Journal of Solid-State Circuits, vol. 42, no. 12, pp. 2745-2757, Dec. 2007.

[3] J. Yang and Y. -b. Kim, "Global clock distribution on standing wave with CMOS active inductor loading," 2017 IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS), Boston, MA, USA, 2017

For more info, check the project's report: (Report)

My project on google drive: (Drive)

Also, Check my notes:
1- Types of Clock Distribution
2- Standing Wave Simulations