SERDES-Design-of-RX-Continuous-time-linear-equalizer

This project shows the design procedure & the testbench setup details used for the design of an Active RX CTLE Equalizer for a 12 Gb/s NRZ input & a channel of 12-inch FR4.

Implementation:

Testbench Schematics:

Frequency Response:

Eye Diagram:

Key References:

[1] B. Razavi, "The Design of an Equalizer—Part One [The Analog Mind]," in IEEE Solid-State Circuits Magazine, vol. 13, no. 4, pp. 7-160, Fall 2021.

[2] S. Gondi and B. Razavi, "Equalization and Clock and Data Recovery Techniques for 10-Gb/s CMOS Serial-Link Receivers," in IEEE Journal of Solid-State Circuits, vol. 42, no. 9, pp. 1999-2011, Sept. 2007.

For design details, check the report: (Report: RX Active CTLE)

For hand analysis example, check the report: (Hand Analysis)

My project on google drive: (Drive)

muhammadaldacher/SERDES-Design-of-RX-Continuous-time-linear-equalizer