Pinned Repositories
-Implementation-of-ANN-to-predict-Handwritten-Language-Using-Verilog
About Implementation of ANN to predict Handwritten Digits using Verilog: Multiplier and Accumulator (MAC), Accumulator(ACC) design, Integrating with sigmoid IP block. Sigmoid is implemented using LUT.
1bit_adder_fpga_verilog
1bit_adder_fpga_verilog
2dconv-FPGA
A 2D convolution hardware implementation written in Verilog
5-Stage-Pipeline-RISC-V-RV32I
The goal of this Project is to design a RISC-V processor with 5 pipeline stages. The version of the RISC-V processor supports only a limited subset of the whole RV32I instruction set, but in the design here reported all the standard instructions except ECALL, EBREAK, and FENCE are implemented.
6T_SRAM
Design, Implementation and Simulation of 6T SRAM Cell under Mixed Signal SOC Design Marathon using eSim & SKY130 by FOSSEE & IITB with Mr. Kunal Ghosh
ACA-CSU_Approximate-Adders
MATLAB and HDL models of ACA-CSU approximate adders
ACArithmeticUnits
Some approximate computing arithmetic units
AccANN
🐆 A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration for *AdderNet*
AccDNN
A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration.
fifo_hardware_fpga
FIFO implemented on FPGA Spartan 6
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