Pinned Repositories
-Implementation-of-ANN-to-predict-Handwritten-Language-Using-Verilog
About Implementation of ANN to predict Handwritten Digits using Verilog: Multiplier and Accumulator (MAC), Accumulator(ACC) design, Integrating with sigmoid IP block. Sigmoid is implemented using LUT.
1bit_adder_fpga_verilog
1bit_adder_fpga_verilog
2dconv-FPGA
A 2D convolution hardware implementation written in Verilog
5-Stage-Pipeline-RISC-V-RV32I
The goal of this Project is to design a RISC-V processor with 5 pipeline stages. The version of the RISC-V processor supports only a limited subset of the whole RV32I instruction set, but in the design here reported all the standard instructions except ECALL, EBREAK, and FENCE are implemented.
6T_SRAM
Design, Implementation and Simulation of 6T SRAM Cell under Mixed Signal SOC Design Marathon using eSim & SKY130 by FOSSEE & IITB with Mr. Kunal Ghosh
ACA-CSU_Approximate-Adders
MATLAB and HDL models of ACA-CSU approximate adders
ACArithmeticUnits
Some approximate computing arithmetic units
AccANN
🐆 A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration for *AdderNet*
AccDNN
A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration.
fifo_hardware_fpga
FIFO implemented on FPGA Spartan 6
mukullokhande99's Repositories
mukullokhande99/aimet
AIMET is a library that provides advanced quantization and compression techniques for trained neural network models.
mukullokhande99/ApproximateMult
ILP-based Synthesized Approximate Multiplier
mukullokhande99/asap7
mukullokhande99/Basic-SIMD-Processor-Verilog-Tutorial
mukullokhande99/Cadence-RTL-to-GDSII-Flow
In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.
mukullokhande99/cva6
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
mukullokhande99/cvw
CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.
mukullokhande99/DALI
A GPU-accelerated library containing highly optimized building blocks and an execution engine for data processing to accelerate deep learning training and inference applications.
mukullokhande99/deepmind-research
This repository contains implementations and illustrative code to accompany DeepMind publications
mukullokhande99/fixedpoint
Chisel Fixed-Point Arithmetic Library
mukullokhande99/gemmlowp
Low-precision matrix multiplication
mukullokhande99/heterosim
mukullokhande99/ICC2_scripts
This repository has a list of collaterals needed for ICC2 workshop. It has a modified version of ORCA which was taped-out by NTI.
mukullokhande99/mempool
A 256-RISC-V-core system with low-latency access into shared L1 memory.
mukullokhande99/MIT-6.5940
All Homeworks for TinyML and Efficient Deep Learning Computing 6.5940 • Fall • 2023 • https://efficientml.ai
mukullokhande99/NeuralNetworks
A resource-conscious neural network implementation for MCUs
mukullokhande99/nn-zero-to-hero
Neural Networks: Zero to Hero
mukullokhande99/once-for-all
[ICLR 2020] Once for All: Train One Network and Specialize it for Efficient Deployment
mukullokhande99/openhardwarelib
Verilog library for ASIC and FPGA designers
mukullokhande99/picorv32
PicoRV32 - A Size-Optimized RISC-V CPU
mukullokhande99/RISC-V-PathPlanner
Implementing a RISC-V CPU in Verilog that can run the Path Planning Algorithm
mukullokhande99/RTL-to-Gates-Synthesis-using-Synopsys-tools
For this assignment, you will become familiar with the VLSI tools you will use throughout this semester, learn how a design “flows” through the toolflow, and practice Verilog coding. Specifically, you will write an RTL model of a GCD circuit, synthesize and place and route the design, simulate at every stage, and analyze power.
mukullokhande99/simodense
Simodense: a RISC-V softcore for custom SIMD instructions
mukullokhande99/SoomRV-Arty
SoomRV on the Arty A7 100T FPGA dev board
mukullokhande99/The-Power-of-TCL
mukullokhande99/TiC-SAT
mukullokhande99/torch-approx
GPU-accelerated Neural Network layers using Approximate Multiplications for PyTorch
mukullokhande99/verilog-axi
Verilog AXI components for FPGA implementation
mukullokhande99/Vitis_Accel_Examples
Vitis_Accel_Examples, various RTL cores
mukullokhande99/vivado-risc-v
Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro