mukullokhande99

-Implementation-of-ANN-to-predict-Handwritten-Language-Using-Verilog

About Implementation of ANN to predict Handwritten Digits using Verilog: Multiplier and Accumulator (MAC), Accumulator(ACC) design, Integrating with sigmoid IP block. Sigmoid is implemented using LUT.

1bit_adder_fpga_verilog

1bit_adder_fpga_verilog

2dconv-FPGA

A 2D convolution hardware implementation written in Verilog

5-Stage-Pipeline-RISC-V-RV32I

The goal of this Project is to design a RISC-V processor with 5 pipeline stages. The version of the RISC-V processor supports only a limited subset of the whole RV32I instruction set, but in the design here reported all the standard instructions except ECALL, EBREAK, and FENCE are implemented.

6T_SRAM

Design, Implementation and Simulation of 6T SRAM Cell under Mixed Signal SOC Design Marathon using eSim & SKY130 by FOSSEE & IITB with Mr. Kunal Ghosh

ACA-CSU_Approximate-Adders

MATLAB and HDL models of ACA-CSU approximate adders

ACArithmeticUnits

Some approximate computing arithmetic units

AccANN

🐆 A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration for *AdderNet*

AccDNN

A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration.

fifo_hardware_fpga

FIFO implemented on FPGA Spartan 6

mukullokhande99/6T_SRAM

Design, Implementation and Simulation of 6T SRAM Cell under Mixed Signal SOC Design Marathon using eSim & SKY130 by FOSSEE & IITB with Mr. Kunal Ghosh

mukullokhande99/adapt

Fast Emulation of Approximate DNN Accelerators in PyTorch

mukullokhande99/caravel_project_1

mukullokhande99/Approximate-Full-Adders

Parameterized versions of popular approximate adders designed with Verilog HDL or System Verilog.

mukullokhande99/approximator-tool

Approximator Tool - Generate Verilog code for approximate adders and multipliers, analyse error and accuracy of approximate circiuts

mukullokhande99/AutoSA

AutoSA: Polyhedral-Based Systolic Array Compiler

mukullokhande99/Booth_Multipliers

Parameterized Booth Multiplier in Verilog 2001

mukullokhande99/cordic

Synthesizable SystemVerilog implementation of fixed-point CORDIC algorithm

mukullokhande99/Cordic-based-CoDesign

A project in which Xilinx's CORDIC (COordinate Rotation DIgital Computer) IP is used as the hardware accelerator and the processor transfers the computational load to the hardware accelerator.

mukullokhande99/deep-compression

Learning both Weights and Connections for Efficient Neural Networks https://arxiv.org/abs/1506.02626

mukullokhande99/ee292d.github.io

mukullokhande99/evoapproxlib

Library of approximate arithmetic circuits

mukullokhande99/fp_alu

mukullokhande99/hardware-tools_forked

List of awesome open source hardware tools

mukullokhande99/jubilant-funicular

mukullokhande99/LIF_ALIF_AELIF

This repository is an implementation of LIF neuron model (Leaky Integrate and Fire), Adaptive LIF and Adaptive Exponential LIF from scratch.

mukullokhande99/log-arithmetic

This is a repository for logarithmic Functional Units

mukullokhande99/LQ-Nets

LQ-Nets: Learned Quantization for Highly Accurate and Compact Deep Neural Networks

mukullokhande99/MachineLearningNotebooks

Python notebooks with ML and deep learning examples with Azure Machine Learning | Microsoft

mukullokhande99/MBA_module

mukullokhande99/mit-han-lab-6s965-fall2022

mukullokhande99/modified_booth

mukullokhande99/noxim

Network on Chip Simulator

mukullokhande99/nsdcs_mul

mukullokhande99/PyTorchMemTracer

Depict GPU memory footprint during DNN training of PyTorch

mukullokhande99/skywater-pdk-sky130-raw-data

Raw data collected about the SKY130 process technology.

mukullokhande99/swayambhu_risc_processor

mukullokhande99/TensorFlow-Transfer-Learning-Image-Classification

Practical Guide to Transfer Learning in TensorFlow for Multiclass Image Classification

mukullokhande99/tinyriscv_arty_100t

tinyriscv for arty a7 100t

mukullokhande99/vsdiat_pd

Inverter