myhdl/myhdl

Issues

• Code generation working on python 3.6 but not 3.11

  #425 opened 3 months ago by bjohan
  2

• Bit indexing may cause deprecation warnings

  #429 opened 4 months ago by zhijieshi
  9

• is it possible to write a testbench.vcd from Cosimulation(...)?

  #420 opened 9 months ago by olisnr
  6

• different python versions

  #414 opened a year ago by olisnr
  14

• cosimulation

  #419 opened a year ago by olisnr
  2

• verilog and VHDL reset from @allways_seq() is strange

  #416 opened a year ago by olisnr
  9

• verliog generation of constants is strange

  #388 opened a year ago by olisnr
  10

• website defekt installaion link ' missing...

  #413 opened a year ago by olisnr
  0

• Error: myhdl.AlwaysCombError: sensitivity list is empty

  #411 opened a year ago by IamJezza
  4

• verify_convert() doesn't appear to work as expected

  #409 opened a year ago by davekeeshan
  3

• Constant value inversion (~0x1, ~0x4523) not working in VHDL

  #405 opened a year ago by davekeeshan
  8

• Python3.7 Deprecation list

  #406 opened a year ago by davekeeshan
  11

• Support for switch in MyHDL

  #386 opened 2 years ago by davekeeshan
  4

• BinOps failing if unsigned assigned to boolean in VHDL

  #403 opened a year ago by davekeeshan
  1

• Migrate PyPi release to github actions

  #393 opened 2 years ago by davekeeshan
  6

• Review Tests Investigate all marked xfail

  #397 opened 2 years ago by davekeeshan
  0

• Dynamic Variable assignment

  #385 opened 2 years ago by davekeeshan
  9

• User Defined code not working (verilog_code/vhdl_code)

  #384 opened 2 years ago by davekeeshan
  9

• ‘Constant’ object has no attribute 'signed'

  #379 opened 2 years ago by BlackJackJam
  5

• how to properly create a (synthesized) parity checker function

  #378 opened 2 years ago by rafaelcorsi
  1

• always_comb sensitivity list is Empty

  #377 opened 2 years ago by PiyushSaini09
  4

• ConcatSignal misbehavior converting to hdl

  #364 opened 2 years ago by rafaelcorsi
  2

• vhdl wrong resize length on port

  #374 opened 2 years ago by rafaelcorsi
  3

• shift_left conversion issue in vhdl

  #367 opened 2 years ago by davekeeshan
  46

• AttributeError: 'Name' object has no attribute 'value'

  #373 opened 2 years ago by Grissess
  9

• Incorrect translation in comparation

  #372 opened 2 years ago by Pusiol
  3

• create infinit delay with delay(-1)

  #370 opened 2 years ago by rafaelcorsi
  1

• move CI from travis to github actions

  #334 opened 2 years ago by jck
  2

• config_sim tracebackup undocumented

  #366 opened 2 years ago by rafaelcorsi
  1

• Conversion failing with Python 3.9

  #350 opened 2 years ago by cfelton
  17

• Convert to verilog and keep parameter name

  #326 opened 4 years ago by kermit0124
  9

• Could you help to check if here is non-blocking or blocking?

  #361 opened 3 years ago by TarzanPan
  1

• Modelsim vlog vcom and vsim clarification

  #360 opened 3 years ago by dmitrii-galantsev
  0

• One-hot state machine conversion to Verilog

  #356 opened 3 years ago by kc64
  0

• Verilog Conversion could handle tuples of quantities convertible to ints

  #349 opened 4 years ago by venks1
  8

• conda-forge package

  #354 opened 3 years ago by davidbrochart
  1

• MEP links in documentation point to old doku locations

  #352 opened 3 years ago by venks1
  1

• traceSignals incorrectly writes real value signal to VCD

  #348 opened 4 years ago by zlobriy
  11

• Asynchronous Reset but not every FF, VHDL

  #346 opened 4 years ago by LarsRlrs
  19

• Support of conversion of slice type

  #332 opened 4 years ago by LarsRlrs
  3

• how to assign input variable to weights of a neural network

  #344 opened 4 years ago by LavanyaMa
  2

• verilog code conversion not showing in the respective folder

  #341 opened 4 years ago by LavanyaMa
  15

• ConversionError: non-boolean argument in logical operator

  #343 opened 4 years ago by LavanyaMa
  2

• Update VCD support for real numbers

  #340 opened 4 years ago by capacollo
  0

• Icarus cosimulation on Windows 10 broken

  #321 opened 5 years ago by philipaxer
  8

• General intbv/modbv simulation mismatches with VHDL when involving resize

  #322 opened 5 years ago by hackfin
  0

• Few lines of example MyHDL on the website frontpage or in the repo's readme

  #325 opened 5 years ago by sneak
  1

• myhdl + icarus: static signals not correct in Python

  #324 opened 5 years ago by bluecmd
  2

• problem with vhdl conversion: to_unsigned used wrong size

  #316 opened 5 years ago by jlusiardi
  1

• AttributeError: 'Name' has no attribute 'obj'

  #314 opened 5 years ago by sww1235
  5