This folder contains the AXI Full Master and Slave Chisel codes created by referring to Xilinx's template AXI protocol Verilog codes that were scavenged off of IPs created in Vivado's IP packager. I do not own the rights for those Verilog codes (obviously) and anything else. You are free to use these codes as you please. For any queries or complaints, contact me at mnanoop2014 at big G.