Mikhail Zakhaov m.zakhao@gmail.com December, 2021
A standalone (NIOS II free) interface in VHDL to the ISP1362 USB device for Altera DE2 Development board.
The interface is designed to enable simple, fast, and reliable communication with DE2 board and replace UART interfaces and NIOS II based designs typically used for this task.
Design is written using techniques from Gaisler Method for writing VHDL
1. Hardware
2. Software
3. Misc
- HARDWARE
Design is written using techniques from Gaisler Method for writing VHDL
-
I/O Interface: For demonstration, the I/O interface is placed in loopback mode - incoming data from Host is echoed back, with the following line inside usb.vhd:
drv_i.io <= drv_o.io; --drv_x.io is of record type, with .RDy and .SData fields --when io.SData is ready, io.RDy will pulse for one clock cycle.
Directory structure:
-
src/ - source files for usb interface
- usb.vhd - top entity
- drv.vhd - usb driver
- hal.vhd - low level interface with ISP1362
- devreq.vhd - handles usb device requests
- isp_inc.vhd - ISP1362 register constants and bitfields
- usb_inc.vhd - usb descriptors and configuration.
- For description of the fields: http://www.beyondlogic.org/usbnutshell/usb1.shtml
-
quartus/ - quartus project files. Quartus 13sp1 (Torrent) was tested with this project
- usb.qpf - Quartus project file
-
sim/ - ModelSim and Active HDL testbenches and simulation files
- SOFTWARE
The software has been tested under Windows 10 x64 21H2.
On the Host PC side, Install the winusb-1.0 driver through Zadig (Following this WinUSB WiKi)
- support/winusb/ - User application based on libusb-win32 API implementing basic loop-back upload/download
- Files:
- usb2/usb2.vcxproj - Visual Studio C++ 2022 project file
- usb2/loopback_test.cpp - sends and receives bytes
- Files:
- MISC
-
support/DE2_NIOS_DEVICE_LED/ - implementation of whats in vhdl, but in C and on nios II processor - for reference
-
support/datasheets/ - Datasheets and programming guides for ISP1362