naithanianshul
Student at NC State University pursuing MS in Computer Engineering
Raleigh, North Carolina
Pinned Repositories
alexi-word-companion
a companion app to build vocabulary
branch-prediction-simulator
A branch prediction simulator with bimodal, gshare and a hybrid predictor that selects between the bimodal and the gshare predictor using a chooser table of 2-bit counters.
cache-and-memory-hierarchy-simulator
Implemention of a flexible cache and memory hierarchy simulator. The cache module also implements the functionality of stream buffers. The caches use Write-Back Write-Allocate (WBWA) write policy and Least-Recently-Used (LRU) replacement policy.
cache-coherence-protocols
A simulator to compare different Coherence protocol optimizations for parallel architecture designs. This project implements a N-processor system with MSI, MSI+BusUpgr and MESI Bus-based Coherence protocols.
CPR-implementation-721sim
Implementing coarse-grain retirement and aggressive register reclamation for Checkpoint Processing and Recovery (CPR) in 721sim
dynamic-instruction-scheduling
A simulator for an out-of-order superscalar processor that fetches and issues N instructions per cycle and models the dynamic scheduling mechanism by assuming perfect caches and perfect branch prediction.
Single-Core-5-stage-MIPS-pipeline-RTL
RTL design of a single core 5-stage MIPS pipeline CPU implementation in Verilog
naithanianshul's Repositories
naithanianshul/alexi-word-companion
a companion app to build vocabulary
naithanianshul/branch-prediction-simulator
A branch prediction simulator with bimodal, gshare and a hybrid predictor that selects between the bimodal and the gshare predictor using a chooser table of 2-bit counters.
naithanianshul/cache-and-memory-hierarchy-simulator
Implemention of a flexible cache and memory hierarchy simulator. The cache module also implements the functionality of stream buffers. The caches use Write-Back Write-Allocate (WBWA) write policy and Least-Recently-Used (LRU) replacement policy.
naithanianshul/cache-coherence-protocols
A simulator to compare different Coherence protocol optimizations for parallel architecture designs. This project implements a N-processor system with MSI, MSI+BusUpgr and MESI Bus-based Coherence protocols.
naithanianshul/CPR-implementation-721sim
Implementing coarse-grain retirement and aggressive register reclamation for Checkpoint Processing and Recovery (CPR) in 721sim
naithanianshul/dynamic-instruction-scheduling
A simulator for an out-of-order superscalar processor that fetches and issues N instructions per cycle and models the dynamic scheduling mechanism by assuming perfect caches and perfect branch prediction.
naithanianshul/Single-Core-5-stage-MIPS-pipeline-RTL
RTL design of a single core 5-stage MIPS pipeline CPU implementation in Verilog