Pinned Repositories
avr_cpu
AVR CPU Core Implementation in Verilog HDL.
pseudo_hdl
Pseudo HDL and its simulator written in Python.
r22sdf
Pipeline FFT Implementation in Verilog HDL
vcd2json
Create WaveJSON from VCD file. WaveDrom can convert it to timing diagram.
nanamake's Repositories
nanamake/r22sdf
Pipeline FFT Implementation in Verilog HDL
nanamake/vcd2json
Create WaveJSON from VCD file. WaveDrom can convert it to timing diagram.
nanamake/avr_cpu
AVR CPU Core Implementation in Verilog HDL.
nanamake/pseudo_hdl
Pseudo HDL and its simulator written in Python.