nandland/spi-master

Issues

• Weird Settings for Clk Speed and CLK_PER_HALF_BIT

  #8 opened 10 months ago by ucycg
  0

• [VHDL] Reading an output signal

  #1 opened 3 years ago by artic92
  4

• Incorrect Type-Conversion?

  #5 opened 3 years ago by MaxClerkwell
  0

• MAX_BYTES_PER_CS parameter's behavior doesn't follow it's description in SPI_Master_With_Single_CS

  #2 opened 4 years ago by vladimirnesterov
  1