nbgrass
I am a student from University of Chinese Academy of Sciences
University of Chinese Academy of Sciences
nbgrass's Stars
ForrestBlue/cortexm0ds
lucky-wfw/ARM_AMBA_Design
Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.
shubhi704/APB-Protocol
jessepalomera/10G_EthernetMAC_SystemVerilog_OOP
Final Project for my course in Advanced Verification with SystemVerilog OOP
courageheart/AMBA_APB_SRAM
AMBA v.3 APB v.1 Specification Complaint Slave SRAM Core design and testbench. The testbench is developed using System Verilog and UVM and can be used as standalone Verification IP (VIP).
GodelMachine/AHB2
AMBA AHB 2.0 VIP in SystemVerilog UVM
seabeam/yuu_ahb
UVM AHB VIP
nelsoncsc/ISP_UVM
A Framework for Design and Verification of Image Processing Applications using UVM
naragece/uvm-testbench-tutorial-simple-adder
A basic testbench made for educational purposes using SystemVerilog and the Universal Verification Methodology
marcoz001/axi-uvm
yet another AXI testbench repo. ;) This is for my UVM practice. https://marcoz001.github.io/axi-uvm/
mayurkubavat/UVM-Examples
UVM examples and projects
funningboy/uvm_axi
uvm AXI BFM(bus functional model)
chenyangbing/Memory
ma6174/vim
vim配置文件和插件(不再维护)
Giftwen/CourseDigitalIC
国科大高等数字集成电路分析与设计课程2022fall
will-zzy/UCAS_CS_Alogrithm_Assignment
国科大2021秋季学期计算机算法设计与分析(陈玉福老师)课程作业相关代码以及说明
krahets/hello-algo
《Hello 算法》:动画图解、一键运行的数据结构与算法教程。支持 Python, Java, C++, C, C#, JS, Go, Swift, Rust, Ruby, Kotlin, TS, Dart 代码。简体版和繁体版同步更新,English version ongoing
nbgrass/AlgorithmsByPython
算法/数据结构/Python/剑指offer/机器学习/leetcode